Wafer–based solar cells aren’t done yet
Source: Solid State Technology, February, 2009
http://www.solid-state.com/display_article/352194/5/none/none/Dept/Wafer%E2%80%93based-solar-cells-aren%E2%80%99t-done-yet
The solar industry’s recent growth spurt has shown that success brings new challenges. Once content to salvage silicon scrap from the integrated circuit industry, wafer–based solar cells have become the largest consumer of high–purity silicon. As a result, manufacturers of wafer–based silicon solar cells are caught between rising raw material costs on one side, and less expensive alternative technologies on the other.
As the name implies, wafer–based silicon cells are fabricated from slices of either single–crystal or multicrystalline silicon. They achieve the highest efficiencies of any commodity photovoltaic technology, second only to cells based on GaAs and other type III–V semiconductors. Single–crystal (c–Si) cells depend on the same Czochralski growth process used to make wafers for integrated circuits, while multicrystalline (mc–Si) cells are cut from cast silicon ingots. Silicon is the largest contributor to the cost of wafer–based cells, accounting for as much as 50% of the total. (Cell cost, in turn, accounts for about half of the total cost of a photovoltaic system.) When the solar energy boom created a severe shortage of high–purity polysilicon, wafer–based cell manufacturers saw their costs rocket upward.
Higher costs created an opportunity for less expensive cells, based on thin films of silicon and other photoactive semiconductors. Though less efficient than wafer–based cells, thin–film cells derive a significant cost advantage by using much smaller quantities of semiconductor. At this writing, industry analysts at SolarBuzz report that the lowest quoted thin–film module price stands at US$3.02 per watt–peak, with the lowest c–Si module at $4.24 per watt–peak.
Manufacturers of wafer–based cells have responded with rapid reductions in silicon consumption. According to Jef Poortmans, director of IMEC’s organic and solar department, current cells use between eight and nine grams of silicon per watt of power generation, with wafer thicknesses in the neighborhood of 200μm. At this spring’s IEEE Photovoltaic Specialists’ Conference (PVSC’08), John Wohlgemuth, staff scientist at BP Solar, reported that his company has qualified modules based on 180μm thick wafers and is testing processes for 160μm thick wafers cut with 100μm wire. IMEC’s roadmap, presented at the organization’s recent annual research review meeting, envisions use of 80μm wafers by 2015.
IMEC’s roadmap for c–Si PV technology. (Source: IMEC)
http://www.solid-state.com/articles/enlarge_image.html?siteId=sst&id=308775
As wafer thickness drops, kerf loss accounts for a larger fraction of silicon consumption. Ultimately, the width of the saw limits the number of wafers that can be cut from a silicon ingot. According to Erik Sauar at the REC Group, speaking at PVSC’08, silicon shortages have driven tremendous improvements in sawing efficiency: manufacturers are obtaining 50% more wafers per ingot than they were as recently as 2005.
Though layer transfer techniques like those used in silicon–on–insulator wafer manufacturing would minimize kerf loss, they are currently too expensive to be practical for solar cells. For example, Soitec’s SmartCut process uses ion implantation to isolate the layer to be transferred from the rest of the wafer, creating the eventual cleavage plane. IMEC’s stress–induced cleaving process, in contrast, deposits a metal layer on the starting wafer. Differential thermal expansion between silicon and the metal literally pulls a silicon layer free, Poortmans said.
Though differential thermal expansion can be useful, as in this technique, it can also pose problems for the solar cell. Metal contacts, particularly the blanket films used for backside contacts, can bend thin wafers, making them more difficult to handle and more susceptible to breakage. Wohlgemuth noted that several suppliers have introduced low–bow aluminum pastes. Though thicker wafers can support themselves, handling becomes much more challenging as wafer thickness goes down. Fully automated wafer handling will likely be required below 160μm, Wohlgemuth said; layers <100μm thick will almost certainly require a glass or plastic carrier substrate during processing.
The photovoltaic industry is seeking to increase automation in order to cut costs, particularly in the module assembly phase. However, automation by itself will not necessarily eliminate cell breakage. The industry does not yet have clear specifications or testing standards for thin wafers. As Poortmans explained, part of IMEC’s research effort focuses on early crack detection, particularly identification of cracks which do not immediately cause an electrical failure, but may become worse with further handling.
Though reducing wafer thickness does not require the wholesale changes typical of new process generations for integrated circuits, thin cells do face performance challenges. One of the most important of these, as described in Solid State Technology (“Improved efficiency boosts PV panel prospects,” Oct. 2008) is the need for a backside reflector to increase light capture. Any such layer will contribute to wafer stress, so thermal budgets and the risk of breakage will require careful consideration. On the other hand, back contact designs benefit from thinner wafers, which reduce resistive losses between the front surface, where carriers are generated, and the contacts.
Eventually, Poortmans said, IMEC hopes to achieve cost–effective epitaxial deposition on glass, combining the cost advantages of thin film deposition with the performance advantages of high–quality silicon, and driving cost below €1/watt.